Semiconductor memories are formed with memory cells that store bits of data. The memory cells are normally very small. As a result, cell data signals that indicate the states of the stored data are electrically small and need to be amplified. Devices commonly referred to as sense amplifiers provide the amplification. A sense amplifier typically amplifies the difference between a data signal received at one input terminal and a reference signal received at another input terminal. Because the cell data signals are small, sense amplifiers must be highly sensitive to correctly read the stored data.
One way to enhance the sensitivity of a sense amplifier is to employ a balanced sensing arrangement that takes advantage of the largely matching impedance characteristics of portions of the circuitry used to access the memory cells. Referring to the drawings, FIG. 1 illustrates a conventional balanced sensing arrangement for a semiconductor memory. The memory circuitry in FIG. 1 consists of memory sections 20 and 22, multiplexers (“MUXes”) 24 and 26, and sense amplifiers 28 that provide data output signals.
Each memory section 20 or 22 consists of an array of memory cells 30 accessed through word lines 32 and bit lines 34. Each memory cell 30 is diagramatically shown as being at the intersection of a word line 32 and a bit line 34. When a word line 32 in section 20 is activated, signals indicative of the data in cells 30 along that word line 32 are provided on associated bit lines 34 to MUX 24 which supplies a subset of the data signals on data lines 36 to sense amplifiers 28. A similar activity occurs when a word line 32 in memory section 22 is activated. Signals indicative of the data in cells 30 along that word line 32 are furnished on associated bit lines 34 to MUX 26 which furnishes a subset of those data signals on data lines 38 to amplifiers 28.
A balanced sensing arrangement is achieved by utilizing one memory section 20 or 22 as a reference array when a word line 32 is activated in the other section 22 or 20 for a read operation. During the read operation, none of cells 32 in the reference array are activated. Substantially no current flows through bit lines 34 in the reference array. However, both of MUXes 24 and 26 are activated so that sense amplifiers 28 are connected by way of data lines 36 to a subset of bit lines 34 in section 20 and by way of data lines 38 to a subset of bit lines 34 in section 22.
The subset of bit lines 34 in memory section 22 presents largely the same impedance as the subset of bit lines 34 in memory section 20. Accordingly, the impedance “seen” by sense amplifiers 28 along data lines 38 and the associated subset of bit lines 34 in section 22 largely matches the impedance “seen” by amplifiers 28 along data lines 36 and the associated subset of bit lines 34 in section 20. Matching impedances at the input terminals to sense amplifiers 28 in this way reduces sensitivity to noise, thereby improving the sensing accuracy. Data lines 36 and 38 are, however, commonly quite long, especially when the memory of FIG. 1 is a large memory. The resultant increased impedance is disadvantageous.
Pitts, U.S. Pat. No. 6,052,308, describes an extension of the balanced sensing arrangement of FIG. 1 to a flash EPROM containing a group of memory arrays whose memory cells are formed with floating-gate field-effect transistors (“FETs”). In a floating-gate FET, a floating gate lies between a control gate and the FET's channel region. An n-channel floating-gate FET is programmed by placing electrons on the floating gate to raise the FET's threshold voltage. When the FET is selected for reading by providing an access voltage between the control gate and the FET's source, the access voltage is less than the threshold voltage so that the FET is turned off. This defines a low logic state commonly referred to as logic “0”. The FET is erased by removing electrons from the floating gate to reduce the threshold voltage. An access voltage applied between the control electrode and the source is then greater than the threshold voltage. The FET turns on and draws substantial current to establish a high logic state commonly referred to as logic “1”.
The floating-gate memory cells utilized in Pitts are of a type subject to an overerasure phenomenon in which the amount of electronic charge removed from a floating gate during erasure is occasionally so great that the cell is turned on even though the cell's word line is not activated. Such an overerased cell draws substantial current. Pitts can eliminate the overerasure by performing a “soft” programming operation on overerased cells. However, if a read operation were performed on one memory section 20 or 22 in FIG. 1 at a time when the other section 22 or 20 contains an overerased cell, i.e., during erasure and/or prior to “soft” programming, the current flowing through the overerased cell could severely damage the sensing accuracy.
Pitts uses an array switching technique to address the overerasure problem. When a memory cell in one of the memory arrays is being read, the EPROM examines a group of associated memory arrays and chooses, as the reference array, an associated array not then undergoing erasure. This is cumbersome because it requires substantial circuitry to perform the array switching. Also, Pitts still needs to perform soft programming whenever overerasure occurs. It would be desirable to have a simple, highly sensitive arrangement for sensing data stored in the cells of a semiconductor memory, especially a flash EPROM of complex architecture.